The traditional testing process does not specifically consider the system performance. With the wide application of parallel testing method, more attention was paid to the system performance and data throughput capacity. Optimizing the software design with multithreading technology becomes an effective way to improve the performance of automatic test system. By modeling testing pipeline process, using asynchronous pipeline design patterns and combining task-oriented concepts, an available test system programming model was proposed. The experiment results prove that the model can significantly shorten the average test time in the ideal case of random input of test tasks. Applying this model to an instance of measuring characteristic parameters of Alternating Current (AC) contactor, the results further indicate that this model can significantly increase the flexibility of test configuration and avoid the complexity of multi-threaded programming.
Abstract: To overcome the shortcoming that random measurement matrix is hard for hardware implementation due to its randomly generated elements, a new structural and sparse deterministic measurement matrix was proposed by studying the theory of measurement matrix in Compressed Sensing (CS). The new matrix was based on parity check matrix in Quasi-Cyclic Low Density Parity Check (QC-LDPC) code over finite field. Due to the good channel decoding performance of QC-LDPC code, the CS measurement matrix based on it was expected to have good performance. To verify the performance of the new matrix, CS reconstruction experiments aiming at one-dimensional signals and two-dimensional signals were conducted. The experimental results show that, compared with the commonly used matrices, the proposed matrix has lower reconstruction error under the same reconstruction algorithm and compression ratio. The proposed method achieves certain improvement (about 0.5-1dB) in Peak Signal-to-Noise Ratio (PSNR). Especially, if the new matrix is applied to hardware implementation, the need for physical storage space and the complexity of the hardware implementation should be greatly reduced due to the quasi-cyclic and symmetric properties in the structure.